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Silicon Labs /EFR32ZG23A020F512GM40 /GPIO_NS /LESENSE_ROUTEEN

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Interpret as LESENSE_ROUTEEN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH0OUTPEN)CH0OUTPEN 0 (CH1OUTPEN)CH1OUTPEN 0 (CH2OUTPEN)CH2OUTPEN 0 (CH3OUTPEN)CH3OUTPEN 0 (CH4OUTPEN)CH4OUTPEN 0 (CH5OUTPEN)CH5OUTPEN 0 (CH6OUTPEN)CH6OUTPEN 0 (CH7OUTPEN)CH7OUTPEN 0 (CH8OUTPEN)CH8OUTPEN 0 (CH9OUTPEN)CH9OUTPEN 0 (CH10OUTPEN)CH10OUTPEN 0 (CH11OUTPEN)CH11OUTPEN 0 (CH12OUTPEN)CH12OUTPEN 0 (CH13OUTPEN)CH13OUTPEN 0 (CH14OUTPEN)CH14OUTPEN 0 (CH15OUTPEN)CH15OUTPEN

Description

LESENSE pin enable

Fields

CH0OUTPEN

CH0OUT pin enable control bit
CH1OUTPEN

CH1OUT pin enable control bit
CH2OUTPEN

CH2OUT pin enable control bit
CH3OUTPEN

CH3OUT pin enable control bit
CH4OUTPEN

CH4OUT pin enable control bit
CH5OUTPEN

CH5OUT pin enable control bit
CH6OUTPEN

CH6OUT pin enable control bit
CH7OUTPEN

CH7OUT pin enable control bit
CH8OUTPEN

CH8OUT pin enable control bit
CH9OUTPEN

CH9OUT pin enable control bit
CH10OUTPEN

CH10OUT pin enable control bit
CH11OUTPEN

CH11OUT pin enable control bit
CH12OUTPEN

CH12OUT pin enable control bit
CH13OUTPEN

CH13OUT pin enable control bit
CH14OUTPEN

CH14OUT pin enable control bit
CH15OUTPEN

CH15OUT pin enable control bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data